1. Field of the Invention
The present invention relates to metal-oxide-semiconductor devices (hereinafter referred to as "MOS devices") such as a MOS field effect transistor (hereinafter referred to as a "MOSFET") and an insulated gate bipolar transistor (hereinafter referred to as an "IGBT").
2. Description of the Related Art
There have been known that a power MOSFET and power IGBT, which belong to the MOS device having a MOS structure on a semiconductor substrate, are controllable with a voltage.
FIG. 5 is a cross-sectional view showing a conventional MOSFET. Referring now to FIG. 5, an n.sup.+ drain layer 2 and an n.sup.- layer 1 on n.sup.+ drain layer 2 constitute a substrate for the semiconductor arrangement of FIG. 5. A p-type base region 17 is in the surface portion of n.sup.- layer 1. A p.sup.+ region 21 is formed partially overlapping p-type base region 17 and more deeply than p-type base region 17. In the surface portion of p-type base region 17, an n.sup.+ source region 6 is formed. A channel portion 7 is in the surface portion of p-type base region 17 extending between n.sup.- layer 1 and n.sup.+ source regions 6. A gate electrode 8 is disposed above channel portion 7 with a gate insulation film 9 interposed therebetween. A source electrode 11 is in contact with p.sup.+ region 21 and n.sup.+ source region 6. An interlayer insulation film 10 on gate electrode 8 insulates source electrode 11 from gate electrode 8. A drain electrode 12 is on the surface of n.sup.+ drain layer 2. A second p.sup.+ region 22 may be formed as surrounded by a dotted curve to secure excellent contact of source electrode 11 and to reduce the influence of the parasitic transistor described later.
The MOSFET of FIG. 5 is manufactured as follows. A semiconductor substrate is prepared by forming a highly resistive n.sup.- layer 1 on an n.sup.+ drain layer 2. A p.sup.+ region 21 is formed by introducing atoms of the third group of elements such as boron (B) into n.sup.- layer 1 by ion implantation or by diffusion. A gate insulation film 9 is deposited on n.sup.- layer 1, and then polycrystalline silicon layer for gate electrode 8 on gate insulation film 9. A window is defined through gate electrode 8 by photolithography, and a p-type base region 17 is formed by diffusion through the window. An n.sup.+ source region 6 is formed by implanting ions of the fifth group of elements such as arsenic (As) by utilizing again gate electrode 8 with the window defined therein as a part of a mask for the ion implantation. Then, the foregoing second p.sup.+ region 22 is formed, if required. The entire surface of the semiconductor structure constructed so far including gate electrode 8 but excluding the portion for a contact hole is covered with an interlayer insulation film 10. Finally, a source electrode 11 is formed on n.sup.+ source region 6, p.sup.+ region 21 and interlayer insulation film 10.
By applying a voltage, positive with respect to source electrode 11, to gate electrode 8, a channel is created in channel portion 7 beneath gate insulation film 9. Electrons are injected through channel portion 7 from n.sup.+ source region 6 to n.sup.- layer 1 to make the MOSFET conductive. By basing gate electrode 8 at a potential same as or negative with respect to the potential of source electrode 11, the MOSFET becomes nonconductive. To say in other words, the MOSFET of FIG. 5 exhibits a switching function.
FIG. 6 is a cross-sectional view showing a conventional IGBT. The IGBT of FIG. 6 is different from the MOSFET of FIG. 5 in that n.sup.+ drain layer 2 of the MOSFET is replaced by a p.sup.+ collector layer 14 in the IGBT, and that an n.sup.+ buffer layer 15 is interposed between p.sup.+ collector layer 14 and n.sup.- layer 1. The p.sup.+ collector layer 14, n.sup.+ buffer layer 15 grown in epitaxy onto p.sup.+ collector layer 14 and n.sup.- layer 1 grown in epitaxy onto n.sup.+ buffer layer 15 constitute a semiconductor substrate for the semiconductor arrangement of FIG. 6. The regions of the IGBT are formed through the similar manufacturing steps as those of the MOSFET. In operating the IGBT, holes injected from p.sup.+ collector layer 14 modulate the conductivity of n.sup.- layer 1 to lower the resistance of n.sup.- layer 1.
In manufacturing the foregoing MOSFET and IGBT, n.sup.+ source region 6 and p-type base region 17 are usually formed by self-alignment using gate electrode 8 for masking. Alternatively, p-type base region 17 may be formed through a photoresist mask, and n.sup.+ source region 6 through a poly-crystalline silicon mask. Still alternatively, n.sup.+ source region 6 and p-type base region 17 may be formed through respective photoresist masks.
When the foregoing MOSFET and IGBT are used in an invertor connected to an inductive load, the devices are often broken down at turning off of the devices through the following mechanism.
FIG. 7 is a cross-sectional view showing a part of the conventional MOSFET and an equivalent circuit thereof. The MOSFET includes a parasitic transistor consisting of n.sup.+ source region 6, p-type base region 17 and n.sup.- layer 1. When the MOSFET is turned off under the inductive load, channel portion 7 becomes nonconductive. In this state, no electrons are injected from n.sup.+ source region 6 to n.sup.- layer 1, and a depletion layer expands into n.sup.- layer 1. Though the voltage applied between the source and drain of the MOSFET rises up to the breakdown voltage of the device, an avalanche current flows to consume the energy stored in the inductive load in the MOSFET. The avalanche current flows through p-type base region 17 beneath n.sup.+ source region 6. If the voltage drop caused by the avalanche current across the lateral resistance of p-type base region 17 is large, the foregoing parasitic transistor turns on to break down the device. To obviate the above described drawbacks and to prevent the parasitic bipolar transistor 30 from turning on, the avalanche current is concentrated into p.sup.+ region 21 and prevented from flowing into p-type base region 17 by setting its breakdown voltage lower than the breakdown voltage of p-type base region 17. If p.sup.+ region 21 is diffused deeply to concentrate the avalanche current thereto, the portion of n.sup.- layer 1 between p.sup.+ region 21 and n.sup.+ drain layer 2 becomes thin. Though the thin n.sup.+ drain layer 2 lowers its breakdown voltage, the path of the injected electrons between channel portion 7 and drain electrode 12 remains unchanged. Therefore, the on-resistance of the device remains unchanged. If n.sup.- layer 1 is thickened corresponding to the increased depth of p.sup.+ region 21 to maintain the rated voltage of the device unchanged, the on resistance of the device increases. To maintain the on-resistance unchanged, the chip size should be widened.